The inexorable pursuit of higher performance analog-to-digital converters (ADCs) is fundamental to progress in direct digital radio-frequency receivers and related instrumentation. Cryogenic superconducting ADCs enable ultrafast switching speed, low power, natural quantization of magnetic flux, quantum accuracy, and low noise, which in turn enable fast and accurate data conversion between the analog and digital domains. Based on rapid single-flux quantum (RSFQ) logic, these integrated circuits are capable of achieving performance levels unattainable by any other technology, as reviewed in O. A. Mukhanov, D. Gupta, A. M. Kadin, and V. K. Semenov, “Superconductor Analog-to-Digital Converters,” Proceedings of the IEEE, vol. 92, pp. 1564-1584, 2004, expressly incorporated herein by reference.
Over the last decade, substantial progress has been made toward building complete cryocooled digital receiver prototypes that use superconductor ADCs. The simplest superconductor ADCs have already demonstrated performance that compare favorably with the best semiconductor ADCs, which employ complex multi-modulator architectures and massive digital post-processing for error correction.
One of the most critical parameters to characterize the performance of an ADC is its dynamic range. Dynamic range of the ADC is bounded by the maximum signal that can be digitized and the quantization noise or device noise floor, whichever is greater. The dynamic range is typically given as a power ratio of the maximum signal to the minimum detectable signal, in dB, and expressed as a maximum signal to noise ratio (SNR). Equivalently, it may be given as the effective number of bits (ENOB) by the standard formula ENOB=(SNR[dB]−1.76)/6.02. A related quantity is the spurious-free dynamic range (SFDR), which is given by the ratio between the full-scale power and the largest nonlinear artifact generated by the data conversion that is present in the output band of the ADC. For high-performance ADCs, it is important to minimize nonlinearities as well as noise. Digital-to-analog converters (DACs) have similar considerations.
Superconductor data converters are based on ideal quantization of magnetic flux in units of the flux quantum Φ0=h/2e=2.07 mV-ps, where h=Planck's constant and e is the charge on the electron. RSFQ circuits transport these single-flux-quanta (SFQ) in voltage pulses of height ˜1 mV and pulsewidth ˜2 ps, such that the area under each pulse is exactly Φ0. In this way, both ADCs and DACs in this technology are practically ideal and linear. Furthermore, SNR and SFDR of broadband superconductor ADCs are among the best in any technology. Still, it is greatly desirable to increase the SNR and SFDR of a superconductor ADC.
One class of ADCs with an extended dynamic range is a subranging ADC, which combines a coarse ADC, a DAC, and a fine ADC used together in a generic architecture as shown in FIG. 1. In a subranging ADC with two ranges, the signal to be digitized is split between a coarse ADC and a fine ADC. See, U.S. Pat. Nos. 7,365,663, 7,362,125, 7,313,199, 7,280,623, 7,038,604, 6,922,066, 6,771,201, 6,750,794, 6,653,962, 6,608,581, 6,509,853, 6,331,805, 6,225,936, 6,127,960, 5,936,458, 5,731,775, 5,305,006, and 5,272,479, expressly incorporated herein by reference.
In the most ideal case, one may be able to double the number of effective bits digitized, sharply increasing the dynamic range. The basic approach, as known in the prior art, involves splitting the incoming analog signal into two parts using an appropriate signal distribution network, one part of which goes to the coarse ADC, which generates a set of digital bits. This digital output is also converted back to an analog signal in a digital to analog converter (DAC), and is combined with the second part of the analog input in a subtractor unit, such that most of the signal should cancel out, leaving only a small residue signal. Accurate cancellation requires that the DAC be substantially accurate and linear, and that an appropriate time delay and linear gain amplifier (or attenuator) be included to ensure that the direct analog signal and the regenerated analog signal are substantially matched. The residue signal can then be amplified in a linear amplifier and fed to the fine ADC, which generates another set of digital bits. The most significant bits (MSBs) are combined with the least significant bits (LSBs) in a digital adder (with appropriate digital delay and digital scaler or multiplier) to generate the combined digital output.
It is important to note that if the DAC is precisely linear and if the gain and delay of the regenerated analog signal are adjusted properly, this subranging ADC can completely compensate for quantization noise and nonlinearity in the coarse ADC. In this case, the performance is limited only by the fine ADC. In the ideal case, with a sharply reduced residue signal, the gain in the amplifier will be large so as to make use of the full input range of the fine ADC, thus gaining additional bits of precision. If one assumes that the full-scale input ranges of the fine ADC and the coarse ADC are the same, and if, for example, the residue signal is a factor of 100 smaller in amplitude than the initial analog signal, then the gain of amplifier could be as high as 100. This, in turn, could lead to an increase in dynamic range for the subranging ADC of as much as this factor of 100, although this would likely be reduced by various non-idealities. In some cases of the prior art, the fine ADC and the coarse ADC may have different input ranges. For example, the fine ADC may be intrinsically more sensitive (reduced full-scale input level and noise level) than the coarse ADC, in which case the required gain of amplifier would be reduced accordingly.
Subranging ADCs have been developed using semiconductor technology of the prior art, including a semiconductor DAC and transistor amplifiers. However, it is well known that semiconductor DACs may exhibit significant nonlinearity, thus limiting the performance of the overall subranging ADC. As a way of avoiding this problem, Hansen and Saxe proposed in U.S. Pat. No. 6,489,913, “Subranging ADC using a sigma-delta converter,” expressly incorporated herein by reference, an alternative design for a subranging ADC as shown in FIG. 2 (taken from this patent). FIG. 2 employs a sigma-delta modulator 12 for the coarse ADC, which generates an oversampled sequence of single-bit output pulses, the low-frequency spectrum of which corresponds to the input analog signal. This oversampled pulse train is filtered in a digital decimation filter 26 to generate a multibit Nyquist-rate digital representation. The function of the DAC is obtained simply by analog filtering the single-bit pulse train with a low-pass filter 18 to remove the high-frequency quantization noise. Since a passive analog filter is typically quite linear, this DAC is also equally linear, enabling improved performance in the subranging ADC. In a further aspect of the design of FIG. 2, the functions from FIG. 1 of the subtractor and the amplifier are combined in a high-gain differential amplifier 22. To the degree that the input analog signal and the coarse regenerated analog signal cancel out, a high linear gain K in this amplifier permits additional bits of precision to be generated by the fine ADC 24.
It is of interest to employ high-performance superconductor ADCs in a similar way to that in Hansen et al., to achieve a subranging ADC with further increased dynamic range. Oversampled superconductor modulators and digital decimation filters are well known in the prior art. Indeed, Gupta proposed in U.S. Pat. No. 6,489,913, “Subranging Technique Using Superconductor Technology”, expressly incorporated herein by reference, how a coarse superconductor ADC and a fine superconductor ADC could be combined to create a subranging superconductor ADC with increased dynamic range. This is shown in FIG. 3, taken from FIG. 18 of Gupta, where a coarse superconductor ADC based on a Superconducting Quantum Interference Device (SQUID) is combined with a similar fine superconductor ADC, and a superconductor DAC, to generate additional bits of precision.
However, superconductor technology does have a serious shortcoming in the absence of a high-gain linear transistor amplifier. While some semiconductor amplifiers can operate at cryogenic temperatures, the impedance and threshold sensitivity are poorly matched to superconductor circuits, making inclusion of a semiconductor amplifier within a superconductor circuit generally impractical. Therefore, high-gain linear amplifiers are difficult to implement in superconductor technology. Furthermore, although transformers are linear and can be used to achieve current gain or voltage gain, as passive devices they are unable to achieve power gain. It is difficult to construct a superconducting subranging ADC without a suitable high-gain amplifier.